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document number: mma65xx rev. 3, 03/2012 freescale semiconductor data sheet: techni cal information ? 2011-2012 freescale semiconducto r, inc. all ri ghts reserved. dual-axis spi inertial sensor mma65xx, a safeassure so lution, is a spi-based, dual-axis, medium-g, over- damped lateral accelerometer designed for use in automotive airbag systems. features ? 80g, 105g or 120g full-scale range, independently specified for each axis ? 3.3v or 5v single supply operation ? spi-compatible serial interface ? 12-bit digital signed or unsigned spi data output ? independent programmable arming functions for each axis ? twelve low-pass filter options, ranging from 50 hz to 1000 hz ? optional offset cancellation with > 6s averaging period and < 0.25 lsb/s slew rate ? pb-free 16-pin qfn, 6 by 6 package referenced documents ? aecq100, revision g, dated may 14, 2007 ( http://www.aecouncil.com/ ) for user register array programming, please consult your freescale representative. ordering information device x-axis range y-axis range shipping MMA6519KW 80g 80g tubes mma6525kw 105g 105g tubes mma6527kw 120g 120g tubes MMA6519KWr2 80g 80g tape & reel mma6525kwr2 105g 105g tape & reel mma6527kwr2 120g 120g tape & reel mma65xx bottom view 16 lead qfn 6 mm by 6 mm case 2086-01
sensor 2 freescale semiconductor, inc. mma65xx figure 1. application diagram table 1. external component recommendations ref des type description purpose c1 ceramic 0.1 f, 10%, 10v minimum, x7r v cc power supply decoupling c2 ceramic 1 f, 10%, 10v minimum, x7r voltage regulator output capacitor (c vreg ) c3 ceramic 1 f, 10%, 10v minimum, x7r voltage regulator output capacitor (c vrega ) c3 c1 c2 v cc mma65xx v cc v reg v rega v ss v pp /test cs sclk mosi miso arm_x arm_y v ssa
sensor freescale semiconductor, inc. 3 mma65xx figure 2. internal block diagram figure 3. device orientation diagram figure 4. part marking sinc filter ? converter compensation low-pass filter oscillator 8 mhz 1 mhz 1 mhz regulator digital x-axis g-cell over-damped arm_y y-axis g-cell over-damped sinc filter compensation low-pass filter cancellation offset arm_x v rega v reg monitor clock v rega v reg v cc iir iir cancellation offset arm_y arm_x cs sclk mosi miso y-axis register array generation clock crc generation clock crc spi y-axis i/o spi mismatch spi x-axis register array verification clock & bias generator ? converter clock & bias generator spi x-axis otp array memory analog regulator self test voltage monitoring linear interpolation linear interpolation output scaling output scaling offset monitor offset monitor v cc v reg v rega v ss x: 0 g y: -1 g earth ground x: +1 g y: 0 g x: 0 g y: +1 g x: -1 g y: 0 g x: 0 g y: 0 g x: 0 g y: 0 g xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx mma65xx(k)w awlywwz data code legend: a: assembly location wl: wafer lot number (g-cell lot number) y: year ww: work week z: assembly lot number
sensor 4 freescale semiconductor, inc. mma65xx 1 pin connections figure 5. top view, 16-pin qfn package v rega v ss n/c v ssa n/c v ssa test/v pp miso mosi sclk v cc v ss v reg arm_x/pcm_x 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 cs arm_y/pcm_y 17 table 2. pin descriptions pin pin name formal name definition 1v rega analog supply this pin is connected to the power supply for the internal analog circuitry. an external capacitor must be connected between this pin and v ssa . reference figure 1 . 2v ss digital gnd this pin is the power suppl y return node for the digital circuitry. 3v reg digital supply this pin is connected to the power s upply for the internal digital circuitr y. an external capacitor must be connected between this pin and v ss . reference figure 1 . 4v ss digital gnd this pin is the power suppl y return node for the digital circuitry. 5 arm_y/ pcm_y y-axis arm output / pcm output the function of this pin is configurable via the devcfg register as described in section 3.1.6.6 . when the arming output is selected, arm_y can be configured as an open drain, active low output with a pullup current; or an open drain, active high output with a pulldown curr ent. alternatively, this pi n can be configured as a digital output with pcm signal proportional to the y axis acceleration data. reference section 3.8.10 and section 3.8.11 . if unused, this pin must be left unconnected. 6 arm_x/ pcm_x x-axis arm output / pcm output the function of this pin is configurable via the devcfg register as described in section 3.1.6.6 . when the arming output is selected, arm_x can be configured as an open drain, active low output with a pullup current; or an open drain, active high output with a pulldown curr ent. alternatively, this pi n can be configured as a digital output with a pcm signal proportional to the x-axis acceleration data. reference section 3.8.10 and section 3.8.11 . if unused, this pin must be left unconnected. 7 test / v pp programming voltage this pin provides the power for factory programming of the otp registers. this pin must be connected to v ss in the application. 8 miso spi data out this pin functions as the serial data output for the spi port. 9v cc supply this pin supplies power to the device. an external capacitor must be connected between this pin and v ss . reference figure 1 . 10 sclk spi clock this input pin provides the serial clock to the spi port. an internal pulldown device is connected to this pin. 11 mosi spi data in this pin functions as t he serial data input to the spi port. an inte rnal pulldown device is connected to this pin. 12 cs chip select this input pin provides the chip select for t he spi port. an internal pullup device is connected to this pin. 13 v ssa analog gnd this pin is the power s upply return node for analog circuitry. 14 nc no connect not internally connected. this pin can be unconnected or connected to v ss in the application. 15 nc no connect not internally connected. this pin can be unconnected or connected to v ss in the application. 16 v ssa analog gnd this pin is the power s upply return node for analog circuitry. 17 pad die attach pad this pin is the die attach flag, and is internally connected to v ss . reference section 5 for die attach pad connection details. corner pads the corner pads are internally connected to v ss .
sensor freescale semiconductor, inc. 5 mma65xx 2 electrical characteristics 2.1 maximum ratings maximum ratings are the extreme limits to which the devi ce can be exposed without permanently damaging it. 2.2 operating range the operating ratings are the limits normally expected in the application and defi ne the range of operation. # rating symbol value unit 1 supply voltage v cc -0.3 to +7.0 v(3) 2 v reg , v rega v reg -0.3 to +3.0 v(3) 3 sclk, cs , mosi,v pp /test v in -0.3 to v cc + 0.3 v(3) 4 arm_x, arm_y v in -0.3 to v cc + 0.3 v(3) 5 miso (high impedance state) v in -0.3 to v cc + 0.3 v(3) 6 powered shock (six sides, 0.5 ms duration) g pms 1500 g (5,18) 7 unpowered shock (six sides, 0.5 ms duration) g shock 2000 g (5,18) 8 drop shock (to concrete surface) h drop 1.2 m(5) 9 10 11 electrostatic discharge human body model (hbm) charge device model (cdm) machine model (mm) v esd v esd v esd 2000 750 200 v v v (5) (5) (5) 12 storage temperature range t stg -40 to +125 c (5) 13 thermal resistance - junction to case q jc 2.5 c/w (14) # characteristic symbol min typ max units 14 15 supply voltage standard operating voltage, 3.3v standard operating voltage, 5.0v v cc v l +3.135 v typ +3.3 +5.0 v h +5.25 v v (15) (15) 16 operating ambient temperature range verified by 100% final test t a t l -40 ? t h +105 c (1) 17 power-on ramp rate (v cc ) v cc_r 0.000033 ? 3300 v/ s (19)
sensor 6 freescale semiconductor, inc. mma65xx 2.3 electrical characteristics - power supply and i/o v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified # characteristic symbol min typ max units 18 supply current * i dd 4.0 ? 8.0 ma (1) 19 20 21 22 23 24 25 26 power supply monitor thresholds (see figure 9 ) v cc under voltage (falling) v reg under voltage (falling) v reg over voltage (rising) v rega under voltage (falling) v rega over voltage (rising) power supply monitor hysteresis v cc under voltage v reg under voltage, v reg over voltage v rega under voltage, v rega over voltage * * * * * v cc_uv_f v reg_uv_f v reg_ov_r v rega_uv_f v rega_ov_r v hyst v hyst v hyst 2.74 2.10 2.65 2.20 2.65 65 20 20 ? ? ? ? ? 100 100 100 3.02 2.25 2.85 2.35 2.85 110 210 150 v v v v v mv mv mv (3,6) (3,6) (3,6) (3,6) (3,6) (3) (3) (3) 27 28 29 power supply reset thresholds (see figure 6 , and figure 9 ) v reg under voltage reset (falling) v reg under voltage reset (rising) v reg reset hysteresis * * v reg_uvr_f v reg_uvr_r v hyst 1.764 1.876 80 ? ? ? 2.024 2.152 140 v v mv (3,6) (3,6) (3) 30 31 internally regulated voltages v reg v rega * * v reg v rega 2.42 2.42 2.50 2.50 2.58 2.58 v v (1,3) (1,3) 32 33 external filter capacitor (c vreg , c vrega ) value esr (including interconnect resistance) c vreg , c vrega esr 700 ? 1000 ? 1500 400 nf m (19) (19) 34 35 power supply coupling 50 khz f n 300 khz 4 mhz f n 100 mhz ? ? ? ? 0.004 0.004 lsb/mv lsb/mv (19) (19) 36 37 output high voltage (miso, pcm_x, pcm_y) 3.15v (v cc - v ss ) 3.45v (i load = -1 ma) 4.75v (v cc - v ss ) 5.25v (i load = -1 ma) * * v oh_3 v oh_5 v cc - 0.2 v cc - 0.4 ? ? ? ? v v (2,3) (2,3) 38 39 output low voltage (miso , pcm_x, pcm_y) 3.15v (v cc - v ss ) 3.45v (i load = 1 ma) 4.75v (v cc - v ss ) 5.25v (i load = 1 ma) * * v ol_3 v ol_5 ? ? ? ? 0.2 0.4 v v (2,3) (2,3) 40 41 open drain output high voltage (arm_x, arm_y) 3.15v (v cc - v ss ) 3.45v (i arm = -1 ma) 4.75v (v cc - v ss ) 5.25v (i arm = -1 ma) * * v odh_3 v odh_5 v cc - 0.2 v cc - 0.4 ? ? ? ? v v (2,3) (2,3) 42 43 open drain output pulldown current (arm_x, arm_y) 3.15v (v cc - v ss ) 3.45v (v arm = 1.5v) 4.75v (v cc - v ss ) 5.25v (v arm = 1.5v) * * i odpd_3 i odpd_5 50 50 ? ? 100 100 a a (2,3) (2,3) 44 45 open drain output low voltage (arm_x, arm_y) 3.15v (v cc - v ss ) 3.45v (i arm = 1 ma) 4.75v (v cc - v ss ) 5.25v (i arm = 1 ma) * * v odh_3 v odh_5 ? ? ? ? 0.2 0.4 v v (2,3) (2,3) 46 47 open drain output pullup current (arm_x, arm_y) 3.15v (v cc - v ss ) 3.45v (v arm = 1.5v) 4.75 v (v cc - v ss ) 5.25v (v arm = 1.5v) * * i odpu_3 i odpu_5 -100 -100 ? ? -50 -50 a a (2,3) (2,3) 48 input high voltage cs , sclk, mosi * v ih 2.0 ? ? v (3,6) 49 input low voltage cs , sclk, mosi * v il ??1.0v(3,6) 50 input voltage hysteresis cs , sclk, mosi * v i_hyst 0.125 ? 0.500 v (19) 51 52 input current high (at v ih ) (sclk, mosi) low (at v il ) (cs) * * i ih i il -70 30 -50 50 -30 70 a a (2,3) (2,3)
sensor freescale semiconductor, inc. 7 mma65xx 2.4 electrical characteristics - sensor and signal chain v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified. # characteristic symbol min typ max units 53 54 55 digital sensitivity (spi) 80g (12-bit output) 105.5g (12-bit output) 120g (12-bit output) * * * sens sens sens ? ? ? 24.0 18.2 16.0 ? ? ? lsb/g lsb/g lsb/g (1,9) (1,9) (1,9) 56 57 58 sensitivity error t a = 25c -40c t a 105c -40c t a 105c,v cc_uv_f v cc - v ss v l * * sens sens sens -4 -5 -5 ? ? ? +4 +5 +5 % % % (1) (1) (3) 59a 60a 61a 62a offset at 0g (105.5g 120g range, no offset cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, v cc_uv_f v cc - v ss v l 12 bits, signed, v cc_uv_f v cc - v ss v l * * offset offset offset offset 1988 -60 1988 -60 2048 0 ? ? 2108 +60 1988 -60 lsb lsb lsb lsb (1) (1) (3) (3) 63a 64a 65a 66a offset at 0g (80g range, no offset cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, v cc_uv_f v cc - v ss v l 12 bits, signed, v cc_uv_f v cc - v ss v l * * offset offset offset offset 1968 -80 1968 -80 2048 0 ? ? 2128 +80 1968 -80 lsb lsb lsb lsb (1) (1) (3) (3) 67b 68b 69b 70b offset at 0g (with offset cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, v cc_uv_f v cc - v ss v l 12 bits, signed, v cc_uv_f v cc - v ss v l * * offset offset offset offset 2047.75 -0.25 2047.75 -0.25 2048 0 ? ? 2048.25 +0.25 2048.25 +0.25 lsb lsb lsb lsb (9,7) (9,7) (9) (9) 71 72 offset monitor thresholds positive threshold (12 bits signed) negative threshold (12 bits signed) offthr pos offthr neg ? ? 100 -100 ? ? lsb lsb (7) (7) 73 74 75 76 range of output (spi, 12 bits, unsigned) normal fault response code unused codes unused codes range fault unused unused 128 ? 1 3969 ? 0 ? ? 3968 ? 127 4095 lsb lsb lsb lsb (7) (7) (7) (7) 77 78 79 range of output (spi, 12 bits, signed) normal unused codes unused codes range unused unused -1920 -2047 1921 ? ? ? 1920 -1921 2047 lsb lsb lsb (7) (7) (7) 80 nonlinearity * nl out -1 ? 1 % fsr (3) 81 82 system output noise rms (12 bits, all ranges, 400 hz, 3-pole lpf) peak to peak (12 bits, al l ranges, 400 hz, 3-pole lpf) n rms n p-p ? ? ? ? 1 3 lsb lsb (3) (3) 83 84 85 86 cross-axis sensitivity v zx v yx v zy v xy * * * * v zx v yx v zy v xy -4 -4 -4 -4 ? ? ? ? +4 +4 +4 +4 % % % % (3) (3) (3) (3)
sensor 8 freescale semiconductor, inc. mma65xx 2.5 self test v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified. # characteristic symbol min typ max units 87 88 89 90 91 92 93 94 95 self test output change (ref section 3.6 ) 80g, t a = 25c 80g, -40c t a 105c 80g, -40c t a 105c, v cc_uv_f v cc - v ss v l 105.5g, t a = 25c 105.5g, -40c t a 105c 105.5g, -40c t a 105c, v cc_uv_f v cc - v ss v l 120g, t a = 25c 120g, -40c t a 105c 120g, -40c t a 105c, v cc_uv_f v cc - v ss v l * * * * * * st 80_25 st 80_ t st 80_ t v st 105_25 st 105_ t st 105_ t v st 120_25 st 120_ t st 120_ t v st min 582 545 545 442 414 414 387 363 363 st nom 727 727 727 553 553 553 484 484 484 st max 872 909 909 663 690 690 581 605 605 lsb lsb lsb lsb lsb lsb lsb lsb lsb (1) (1) (3) (1) (1) (3) (1) (1) (3) 96 97 self test cross-axis output y-axis output with x-axis self test x-axis output with y-axis self test stcrossaxis stcrossaxis -10 -10 ? ? +10 +10 lsb lsb (1) (1) 98 99 self test output accuracy from stored value, including sensitivity error -40c ta 105c (ref section 3.6) * stacc -10 ? +10 % (3) 100 sigma delta modulator range x/y-axis, any range positive/negative g adcl_clip 375 400 450 g (19) 101 acceleration (without hitting internal g-cell stops) x/y-axis, any range positive/negative g g-cell_clip 500 560 600 g (19)
sensor freescale semiconductor, inc. 9 mma65xx 2.6 dynamic electrical characteristics - signal chain v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified. # characteristic symbol min typ max units 102 103 104 dsp sample rate (lpf 0,1,2,3,4,5) dsp sample rate (lpf 8,9,10,11,12,13) interpolation sample rate t s t s t interp ? ? ? 64/f osc 128/f osc t s /2 ? ? ? s s s (7) (7) (7) 105 106 data path latency (excluding g-cell and low pass filter) t s = 64/f osc t s = 128/f osc * * t datapath_8 t datapath_16 33.0 51.9 34.8 54.6 36.5 57.4 s s (7,16) (7,16) 107 108 109 110 111 112 low-pass filter (t s = 8 s) cutoff frequency 0: 100 hz, 4-pole cutoff frequency 1: 300 hz, 4-pole cutoff frequency 2: 400 hz, 4-pole cutoff frequency 3: 800 hz, 4-pole cutoff frequency 4: 1000 hz, 4-pole cutoff frequency 5: 400 hz, 3-pole * * * * * * f c0(lpf) f c1(lpf) f c2(lpf) f c3(lpf) f c4(lpf) f c5(lpf) 95 285 380 760 950 380 100 300 400 800 1000 400 105 315 420 840 1050 420 hz hz hz hz hz hz (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) 113 114 115 116 117 118 low-pass filter (t s = 16 s) cutoff frequency 8: 50 hz, 4-pole cutoff frequency 9: 150 hz, 4-pole cutoff frequency 10: 200 hz, 4-pole cutoff frequency 11: 400 hz, 4-pole cutoff frequency 12: 500 hz, 4-pole cutoff frequency 13: 200 hz, 3-pole * * * * * * f c8(lpf) f c9(lpf) f c10(lpf) f c11(lpf) f c12(lpf) f c13(lpf) 47.5 142.5 190 380 475 190 50 150 200 400 500 200 52.5 157.5 210 420 525 210 hz hz hz hz hz hz (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) 119 120 121 122 123 124 125 offset cancellation (normal mode, 12-bit output) offset averaging period offset slew rate offset update rate offset correction value per update positive offset correction value per update negative offset correction threshold positive offset correction threshold negative * * * * * * * off aveper off slew off rate off corrp off corrn off thp off thn ? ? ? ? ? ? ? 6.29146 0.2384 1049 0.25 -0.25 0.125 0.125 ? ? ? ? ? ? ? s lsb/s ms lsb lsb lsb lsb (3,7) (3,7) (3,7) (3,7) (3,7) (3,7) (3,7) 126 127 128 129 130 131 self test activation time (cs rising edge to 90% of st final value) cutoff frequency 0: 100 hz, 4-pole cutoff frequency 1: 300 hz, 4-pole cutoff frequency 2: 400 hz, 4-pole cutoff frequency 3: 800 hz, 4-pole cutoff frequency 4: 1000 hz, 4-pole cutoff frequency 5: 400 hz, 3-pole st_act 100 st_act 300 st_act 400 st_act 800 st_act 1000 st_act 400_3 ? ? ? ? ? ? ? ? ? ? ? ? 7.00 3.00 2.50 1.70 1.60 2.40 ms ms ms ms ms ms (19) (19) (19) (19) (19) (19) 132 offset monitor bypass time a fter self test deactivation t st_omb ? 320 ? t s (3,7) 133 time between acceleration data requests (same axis) t acc_req 15 ? ? s (3,7,20) 134 135 136 arming output activation time (arm_x, arm_y, i arm = 200 a) moving average and count arming modes (2,3,4,5) unfiltered mode activation delay (reference figure 30 ) unfiltered mode arm assertion time (reference figure 30 ) t arm t arm_uf_dly t arm_uf_assert 0 0 5.00 ? ? ? 1.51 1.51 6.579 s s s (3,12) (3,12) (3) 137 sensing element natural frequency f gcell 10791 13464 15879 hz (19) 138 sensing element cutoff frequency (-3 db ref. to 0 hz) f gcell 0.851 1.58 2.29 khz (19) 139 sensing element damping ratio gcell 2.46 4.31 9.36 ? (19) 140 sensing element delay (@100 hz) f gcell_delay 70 101 187 s (19) 141 sensing element step response (0% - 90%) t step_gcell ? ? 200 s (19) 142 package resonance frequency f package 100 ? ? khz (19) 143 package quality factor q package 1 ? 5 (19)
sensor 10 freescale semiconductor, inc. mma65xx 2.7 dynamic electrical char acteristics - supply and spi v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified 1. parameters tested 100% at final test. 2. parameters tested 100% at wafer probe. 3. parameters verified by characterization 4. (*) indicates a crit ical characteristic. 5. verified by qualification testing. 6. parameters verified by pass/fail testing in production. 7. functionality verified 100% via scan. ti ming characteristic is directly determined by in ternal oscillator frequency. 8. n/a 9. devices are trimmed at 100 hz with 1000 hz low-pass filter option selected. response is corrected to 0 hz response. 10.low-pass filter cutoff frequencies shown ar e -3 db referenced to 0 hz response. 11.power supply ripple at frequencies greater than 900 kh z should be minimized to t he greatest extent possible. 12.time from falling edge of cs to arm_x, arm_y output valid 13.n/a 14.thermal resistance between the die junction and the ex posed pad; cold plate is attached to the exposed pad. 15.device characterized at all values of v l & v h . production test is conducted at all typical voltages (v typ ) unless otherwise noted. 16.data path latency is the signal latency from g-ce ll to spi output disregarding filter group delays. 17.filter characteristics are specified independently, and do not include g-cell frequency response. 18.electrostatic deflection test completed during wafer probe. 19.verified by simulation. 20.acceleration data request timing constraint only applies for proper operation of the arming function # characteristic symbol min typ max units 144 145 146 power-on recovery time (vcc = vccmin to first spi access) power-on recovery time (inter nal por to first spi access) spi reset activation time (cs high to reset) t op t op t spi_reset ? ? ? ? ? ? 10 840 300 ms s ns (3) (3,7) (7) 147 148 internal oscillator frequency test frequency - divided from internal oscillator *f osc f osctst 7.6 0.95 8 1 8.4 1.05 mhz mhz (7) (1) 149 serial interface timing (see figure 7 , c miso 80pf, r miso 10kw) clock (sclk) period (10% of v cc to 10% of v cc )* t sclk 120 ? ? ns (3) 150 clock (sclk) high time (90% of v cc to 90% of v cc ) *t sclkh 40 ? ? ns (3) 151 clock (sclk) low time (10% of v cc to 10% of v cc ) *t sclkl 40 ? ? ns (3) 152 clock (sclk) rise time (10% of v cc to 90% of v cc ) t sclkr ?1540ns(19) 153 clock (sclk) fall time (90% of v cc to 10% of v cc ) t sclkf ?1528ns(19) 154 cs asserted to sclk high (cs = 10% of v cc to sclk = 10% of v cc ) t lead 60 ? ? ns (3) 155 cs asserted to miso valid (cs = 10% of v cc to miso = 10/90% of v cc ) t access ??60ns(3) 156 data setup time (mosi = 10/90% of v cc to sclk = 10% of v cc ) *t setup 20 ? ? ns (3) 157 mosi data hold time (sclk = 90% of v cc to mosi = 10/90% of v cc ) *t hold_in 10 ? ? ns (3) 158 miso data hold time (sclk = 90% of v cc to miso = 10/90% of v cc ) *t hold_out 0??ns(3) 159 sclk low to data valid (sclk = 10% of v cc to miso = 10/90% of v cc ) *t valid ??35ns(3) 160 sclk low to cs high (sclk = 10% of v cc to cs = 90% of v cc ) *t lag 60 ? ? ns (3) 161 cs high to miso disable (cs = 90% of v cc to miso = hi z) *t disable ??60ns(3) 162 cs high to cs low (cs = 90% of v cc to cs = 90% of v cc ) *t csn 526 ? ? ns (3) 163 sclk low to cs low (sclk = 10% of v cc to cs = 90% of v cc ) *t clkcs 50 ? ? ns (3) 164 cs high to sclk high (cs = 90% of v cc to sclk = 90% of v cc ) t csclk 50 ? ? ns (19)
sensor freescale semiconductor, inc. 11 mma65xx figure 6. power-up timing figure 7. serial interface timing v cc por v rega v reg devres v cc_uv_f v rega_uv_f devres flag cleared by user v cc_uv_r v rega_uv_r v reg_uvr_r v reg_uvr_f time note: v rega & v reg rise and fall slopes will be dependent on output capacitance and load current t sclk sclk mosi cs miso t sclkh t sclkl t access t sclkr t sclkf t lead t csn t setup t hold_in t valid t disable t hold_out t lag t clkcs t csclk
sensor 12 freescale semiconductor, inc. mma65xx 3 functional description 3.1 customer accessible data array a customer accessible data array allows for each device to be customized. the array consists of an otp factory programma- ble block and read/write registers for device programmability and status. the otp and writable register blocks incorporate inde - pendent crc circuitry for fault detection (reference section 3.2 ). the writable register block includes a locking mechanism to prevent unintended changes during normal operation. portions of the array are reserved for factory-programmed trim values. the customer accessible data is shown in the table below. type codes f: factory programmed otp location r/w: read/write register r: read-only register n/a: not applicable table 3. customer accessible data location bit function type a d d r r e g i s t e r76543210 $00 sn0 sn[7] sn[6] sn[5] sn[4] sn[3] sn[2] sn[1] sn[0] f $01 sn1 sn[15] sn[14] sn[13] sn[12] sn[11] sn[10] sn[9] sn[8] $02 sn2 sn[23] sn[22] sn[21] sn[20] sn[19] sn[18] sn[17] sn[16] $03 sn3 sn[31] sn[30] sn[29] sn[28] sn[27] sn[26] sn[25] sn[24] $04 stdefl_x stdefl_x[7] stdefl_x[6] stdefl_x[5] stdefl_x[4] stdefl_x[3] stdefl_x[2] stdefl_x[1] stdefl_x[0] $05 stdefl_y stdefl_y[7] stdefl_y[6] stdefl_y[5] stdefl_y[4] stdefl_y[3] stdefl_y[2] stdefl_y[1] stdefl_y[0] $06fctcfg_x10000001 $07 fctcfg_y 1 0 0 0 0 0 0 1 $08 pn pn[7] pn[6] pn[5] pn[4] pn[3] pn[2] pn[1] pn[0] $09 invalid address: ?invalid register request? $0a devctl res_1 res_0 ocphase[1] ocphase[0] offcfg_en reserved reserved reserved r/w $0b devcfg oc reserved endinit sd ofmon a_cfg[2] a_cfg[1] a_cfg[0] $0c devcfg_x st_x reserved reserved reserved lpf_x[3] lpf_x[2] lpf_x[1] lpf_x[0] $0d devcfg_y st_y reserved reserved reserved lpf_y[3] lpf_y[2] lpf_y[1] lpf_y[0] $0e armcfgx reserved reserved aps_x[1] aps_x[0] aws_xn[1] aws_xn[0] aws_xp[1] aws_xp[0] $0f armcfgy reserved reserved aps_y[1] aps_y[0] aws_yn[1] aws_yn[0] aws_yp[1] aws_yp[0] $10 armt_xp at_xp[7] at_xp[6] at_xp[5] at_xp[4] at_xp[3] at_xp[2] at_xp[1] at_xp[0] $11 armt_yp at_yp[7] at_yp[6] at_yp[5] at_yp[4] at_yp[3] at_yp[2] at_yp[1] at_yp[0] $12 armt_xn at_xn[7] at_xn[6] at_xn[5] at_x n[4] at_xn[3] at_xn[2] at_xn[1] at_xn[0] $13 armt_yn at_yn[7] at_yn[6] at_yn[5] at_yn[4] at_yn[3] at_yn[2] at_yn[1] at_yn[0] $14 devstat unused ide unused devinit misoerr off_y off_x devres r $15 count count[7] count[6] count[5] count[4] count[3] count[2] count[1] count[0] $16 offcorr_x offcorr_x[7] offcorr_x[6] o ffcorr_x[5] offcorr_x[4] offcorr_x[3] o ffcorr_x[2] offcorr_x[1] offcorr_x[0] $17 off_corr_y offcorr_y[7] offcorr_y[6] offcorr_y[5] offcorr_y[4] offcorr_y[3] offcorr_y[2] offcorr_y[1] offcorr_y[0] $1c reserved reserved reserved reserved reserved reserved reserved reserved reserved $1d reserved reserved reserved reserved reserved reserved reserved reserved reserved
sensor freescale semiconductor, inc. 13 mma65xx 3.1.1 device serial number registers a unique serial number is programmed into the serial number re gisters of each device during manufacturing. the serial num- ber is composed of the following information: serial numbers begin at 1 for all produced devices in each lo t, and are sequentially assigned. lot numbers begin at 1 and are sequentially assigned. no lot will contain more devices than can be uniquely identified by the 13-bit serial number. depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. the serial number registers are included in the otp shadow register array crc verification. reference section 3.2.1 for de- tails regarding the crc verification. beyond this, the contents of the serial number registers have no impact on device operati on or performance, and are only used for traceability purposes. 3.1.2 self test deflection registers (stdefl_x, stdefl_y) these read-only registers provide the nominal self test deflection values for each axis at ambient temperat ure. the self test value is a positive deflection value, measur ed at the factory, and factory programmed for each device. the minimum stored value ($00) equates to the minimum deflection specified in section 2.4 ( st min ), and the maximum stored value ($ff) equates to the maximum deflection specified in section 2.4 ( st max ). when self test is activated, the acceleration reading can be co mpared to the value in this register. the difference from the measured deflection value, and the nominal deflection value stored in the register shall not fall outside the self test accurac y limits specified in section 2.4 ( st acc ). reference section 3.6 for more details on calculat ing the self test limits. 3.1.3 factory configuration registers the factory configuration registers are one time programmable, read only registers which cont ain customer specific device configuration information that is programmed by freescale. bit range content s12 - s0 serial number s31 - s13 lot number table 4. self test deflection registers location bit a d d r e s sr e g i s t e r76543210 $04 stdefl_x stdefl_x[7] stdefl_x[6] stdefl_x[5] stdef l_x[4] stdefl_x[3] stdefl_x[2] stdefl_x[1] stdefl_x[0] $05 stdefl_y stdefl_y[7] stdefl_y[6] stdefl_y[5] stdef l_y[4] stdefl_y[3] stdefl_y[2] stdefl_y[1] stdefl_y[0] table 5. factory configuration register location bit a d d r e s sr e g i s t e r76543210 $ 0 6f c t c f g _ x10000001 $ 0 7f c t c f g _ y10000001
sensor 14 freescale semiconductor, inc. mma65xx 3.1.4 part number register (pn) the part number register is a one time programmable, read only register which contai ns two digits of the device part number to identify the axis and range information. the contents of this register have no impact on device operation or performance. 3.1.5 device control register (devctl the device control register is a read-write register which contai ns device control operations. the upper 2 bits of this registe r can be written during both initialization and normal operation. bits 5 through 0 can be programmed during initialization and th en are ignored once the endinit bit is set. 3.1.5.1 reset control (res_1, res_0) a series of three consecutive register writ e operations to the reset control bits in the devctl register will cause a device re set. to reset the internal digital circuitry, the following register write operations must be performed in the order shown below. th e reg- ister write operations must be consecutive spi commands in the order shown or the device will not be reset. the response to the register write returns ?0? for res_1 and res_0, and the existing register value bits 5 through 0. a reg- ister read of res_1 and res_0 returns ?0? and terminates the reset sequence. if endinit is cleared, the bits 2 through 0 in the devctl register are modified as described in section 4.4 . if endinit is set, a register writ e will not modify bits 2 through 0 and the response to a register read or write will include the last successful writte n values for these bits. table 6. part number register location bit a d d r e s sr e g i s t e r76543210 $08 pn pn[7] pn[6] pn[5] pn[4] pn[3] pn[2] pn[1] pn[0] pn register value x-axis range section 2.4 y-axis range section 2.4 decimal hex 219 $db 80 80 225 $e1 105 105 227 $e3 120 120 table 7. device control register location bit address register 7 6 5 4 3 2 1 0 $0a devctl res_1 res_0 ocphase[1] ocphase[0] offcfg_en reserved r eserved reserved r e s e t v a l u e00000000 register write to devctl res_1 res_0 effect spi register write 1 0 0 no effect spi register write 2 1 1 no effect spi register write 3 0 1 device reset
sensor freescale semiconductor, inc. 15 mma65xx 3.1.5.2 offset cancellation ph ase control bits (ocphase[1:0]) the offset cancellation phase control bits control the offset cancellation start up phase. these bits can be written at any tim e endinit is ?0? if the offcfg_en bit is set. when endinit is set, the ocphase[ 1:0] bits in a write command are ignored and the offset cancellation phase is set to ?nor- mal?. this can only be changed by a device reset. the response to a register read or write of the devctl register once endinit is set will return the last successfu lly written values of ocphase[1:0]. 3.1.5.3 offset cancellation configuration enable bit (offcfg_en) the offset cancellation phase configuration enable bit enables modification of the offset cancellation phase control bits (ocphase[1:0]) as shown in section 3.1.5.2 when endinit is set, the offcfg_en bit in a write command is ignored, and the offset cancellation phase is set to ?normal?. this can only be changed by a device reset. the response to a register read or write of the devctl regist er once endinit is set will return the last successfu lly written value of offcfg_en. 3.1.5.4 reserved bits (devctl[2:0]) bits 2 through 0 of the devctl register are reserved. a write to the reserved bits must always be logic ?0? for normal device operation and performance. 3.1.6 device configuration register (devcfg) the device configuration register is a read/write register which contains data for ge neral device configuration. the register c an be written during initialization but is locked once the endinit bi t is set. this register is in cluded in the writable register crc check. refer to section 3.2.2 for details. 3.1.6.1 offset cancelled data selection bits (oc ) the offset cancelled data selection bit determines whether th e spi transmitted data is raw data or offset cancelled data. if the oc bit is cleared (offset cancelled data), then the offset mo nitor is automatically enabled (ofmon = ?1?) regardless of the value written to devcfg[3]. 3.1.6.2 reserved bit (reserved) bits 6 of the devcfg register is reserv ed. a write to the reserved bit must always be logic ?0? for normal device operation and performance. offcfg_en ocphase[1] ocphase[0] writes to ocphase[1:0] offset cancellation phase 0 don?t care don?t care ignored continues from the previously wr itten phase (ocphase[1:0]) as specified in section 3.8.4 . 1 0 0 accepted remains in start 1 until offcfg_en is cleared or endinit is set 1 0 1 accepted remains in start 2 until offcfg_en is cleared or endinit is set 1 1 0 accepted remains in start 3 until offcfg_en is cleared or endinit is set 1 1 1 accepted remains in normal mode until of fcfg_en is cleared or endinit is set table 8. device configuration register location bit a d d r e s sr e g i s t e r76543210 $0b devcfg oc reserved endinit sd ofmon a_cfg[2] a_cfg[1] a_cfg[0] r e s e t v a l u e 00000000 oc spi data 0 offset cancelled 1 raw data
sensor 16 freescale semiconductor, inc. mma65xx 3.1.6.3 end of initialization bit (endinit) the endinit bit is a control bit used to indicate that the user has completed all device and system leve l initializa tion tests, and that the device will operate in normal mo de. once the endinit bit is set, writes to all writable register bits are inhibite d except for the devctl register. once written, the endinit bit can only be cleared by a device reset. the writable register crc check (reference section 3.2.2 ) is only enabled when the endinit bit is set. when endinit is set, the following occurs: ? offset cancellation is forced to normal mode. ocphase[1:0 ], and offcfg_en remain in their previously set states. ? x-axis self test is disabled. st_x remains in its previously set states. ? y-axis self test is disabled. st_y remains in its previously set states. 3.1.6.4 sd bit the sd bit determines the format of acce leration data results. if the sd bit is set to a logic ?1?, unsigned results are transmitted, with the zero-g level represented by a nominal value of 512. if the sd bit is cleared, signed results are transmitted, with the zero- g level represented by a nominal value of 0. 3.1.6.5 ofmon bit the ofmon bit determines if the offset monitor circuit is enabled. if the ofmon bit is set to a logic ?1?, the offset monitor i s enabled. reference section 3.8.5 . if the ofmon bit is cleared, the offset monitor is disabled. if the oc bit in the devcfg register is cleared (offset cancelled data), then the offset monito r is automatically enabled (of- mon = ?1?) regardless of the value written to devcfg[3]. 3.1.6.6 arm configurat ion bits (a_cfg[2:0]) the arm configuration bits (a_cfg[2:0]) select the m ode of operation for the arm_ x/pcm_x, arm_y/pcm_y pins. sd operating mode 1 unsigned data output 0 signed data output ofmon operating mode 1 offset monitor circuit enabled 0 offset monitor circuit disabled table 9. arming output configuration a_cfg[2] a_cfg[1] a-cfg[0] operating mode output type reference 0 0 0 arm output disabled hi impedance 0 0 1 pcm output digital output section 3.8.11 0 1 0 moving average mode active high with pulldown current section 3.8.10.1 0 1 1 moving average mode active low with pullup current section 3.8.10.1 1 0 0 count mode active high with pulldown current section 3.8.10.2 1 0 1 count mode active low with pullup current section 3.8.10.2 1 1 0 unfiltered mode active high with pulldown current section 3.8.10.3 1 1 1 unfiltered mode active low with pullup current section 3.8.10.3
sensor freescale semiconductor, inc. 17 mma65xx 3.1.7 axis configuration registers (devcfg_x, devcfg_y) the axis configuration registers are read/w rite registers which contain axis specific configuration information. these register s can be written during initialization, but are locked once the endinit bit is set. these registers are included in the writable register crc check. refer to section 3.2.2 for details. 3.1.7.1 self test control (st_x, st_y) the st_x and st_y bits enable and disable the self test circuitr y for their respective axes. self test circuitry is enabled if a logic ?1? is written to st_x, or st_y and the endinit bit has not been se t. enabling the self test circuitry results in a posit ive acceleration value on the enabled axis. self test deflection values are specified in section 2.4 . st_x and st_y are always cleared following internal reset. when the self test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the stat us bits in the acceleration data request response will indicate ?self test active?. reference section 3.8.4 and section 4.2 for de- tails. when the self test circuitry is disabled by clearing the st _x or st_y bit, the offset monitor remains disabled until the time t st_omb specified in section 2.6 expires. however, the status bits in the a cceleration data request response will immediately indicate that self test is deactivated. when endinit is set, self test is disa bled. this can only be changed by a reset. a register write will not modify the st_x and st_y bits and the response to a register read or writ e will include the last successful written values for these bits. 3.1.7.2 reserved bits (reserved) bits 6 through 4 of the devcfg_x and devc fg_y registers are reserved. a write to the reserved bits must always be logic ?0? for normal device operation and performance. 3.1.7.3 low-pass filter selection bits (lpf_x[3:0], lpf_y[3:0]) the low pass filter selection bits independently select a low-pass filter for each axis as shown in ta b l e 11 . refer to section 3.8.3 for details regarding filter configurations. note: filter characteristics do not include g-cell frequency response. table 10. axis configuration registers location bit a d d r e s sr e g i s t e r76543210 $0c devcfg_x st_x reserved reserved reserved lpf_x[3] lpf_x[2] lpf_x[1] lpf_x[0] $0d devcfg_y st_y reserved reserved reserved lpf_y[3] lpf_y[2] lpf_y[1] lpf_y[0] r e s e t v a l u e 00000000 table 11. low pass filter selection bits lpf_x[3] / lpf_y[3] lpf_x[2] / lpf_y[2] lpf_x[1] / lpf_y[1] lpf_x[0] / lpf_y[0] low pass filter selected nominal sample rate ( s) 0000 1 0 0 h z , 4 - p o l e 8 0001 3 0 0 h z , 4 - p o l e 8 0010 4 0 0 h z , 4 - p o l e 8 0011 8 0 0 h z , 4 - p o l e 8 0100 1000 hz, 4-pole 8 0101 4 0 0 h z , 3 - p o l e 8 0110 r e s e r v e d r e s e r v e d 0111 r e s e r v e d r e s e r v e d 1000 5 0 h z , 4 - p o l e 1 6 1001 1 5 0 h z , 4 - p o l e 1 6 1010 2 0 0 h z , 4 - p o l e 1 6 1011 4 0 0 h z , 4 - p o l e 1 6 1100 5 0 0 h z , 4 - p o l e 1 6 1101 2 0 0 h z , 3 - p o l e 1 6 1110 r e s e r v e d r e s e r v e d 1111 r e s e r v e d r e s e r v e d
sensor 18 freescale semiconductor, inc. mma65xx 3.1.8 arming configuration registers (armcfgx, armcfgy) the arming configuration registers contain co nfiguration information for the arming func tion. the values in these registers are only relevant if the arming function is oper ating in moving average mode, or count mode. these registers can be written during initialization but are locked once the endinit bit is set. refer to section 3.1.6.3 . these registers are included in the writable register crc check. refer to section 3.2.2 for details. 3.1.9 reserved bits (reserved) bits 7 through 6 of the armcfgx and armcfgy registers are reserved. a write to the reserved bits must always be logic ?0? for normal device operation and performance. 3.1.9.1 arming pulse stretc h (aps_x[1:0], aps_y[1:0]) the aps_x[1:0] and aps_y[1:0] bits se t the programmable pulse stretch time for the arming outputs. refer to section 3.8.10 for more details regarding the arming function. pulse stretch time s are derived from the internal oscillator, so the tolerance on this oscillator applies. 3.1.9.2 arming window size (aws_xx[1:0], aws_yx[1:0]) the aws_xx[1:0] & aws_yx[1:0] bits have different functions depending on the state of the a_cfg bits in the devcfg reg- ister. if the arming function is set to moving average mode, th e aws bits set the number of acceleration samples used for the arming function moving average. the number of samples is set independently for each axis and polarity. if the arming function is set to count mode, the aws bits set the sample count limit for the arming function. the sample count limit is set independen tly for each axis. refer to section 3.8.10 for more details regarding the arming function. table 12. arming configuration register location bit a d d r e s sr e g i s t e r76543210 $0e armcfgx reserved reserved aps_x[1] aps_x[ 0] aws_xn[1] aws_xn[0] aws_xp[1] aws_xp[0] $0f armcfgy reserved reserved aps_y[1] aps_y[ 0] aws_yn[1] aws_yn[0] aws_yp[1] aws_yp[0] r e s e t v a l u e 00001111 table 13. arming pulse stretch definitions aps_x[1], aps_y[1] aps_x[0] , aps_y[0] pulse stretch time (typical oscillator) 00 0 m s 0 1 16.256 ms - 16.384 ms 1 0 65.408ms - 65.536 ms 1 1 261.888ms - 262.016 ms table 14. x-axis positive arming window size definitions (moving average mode) aws_xp[1] aws_xp[0] x-axis positive window size 00 2 01 4 10 8 11 1 6 table 15. x-axis negative arming window size definitions (moving average mode) aws_xn[1] aws_xn[0] x-axis negative window size 00 2 01 4 10 8 11 1 6
sensor freescale semiconductor, inc. 19 mma65xx 3.1.10 arming threshold registers (armt_xp, armt_xn, armt_yp, armt_yn) the arming threshold registers contain the x-axis and y-axis posi tive and negative thresholds to be used by the arming func- tion. refer to section 3.8.10 for more details regarding the arming function. the arming threshold registers can be written during initia lization but are locked once the endinit bit is set. refer to section 3.1.6.3 . the arming threshold registers are included in the writable register crc check. refer to section 3.2.2 for details. table 16. y-axis positive arming window size definitions (mo ving average mode) aws_yp[1] aws_yp[0] y-axis positive window size 00 2 01 4 10 8 11 1 6 table 17. y-axis negative arming window size definitions (moving average mode) aws_yn[1] aws_yn[0] y-axis negative window size 00 2 01 4 10 8 11 1 6 table 18. arming count limit definitions (count mode) aws_xn[1] aws_xn[0] aws_xp[1] aws_x p[0] x-axis sample count limit don?t care don?t care 0 0 1 don?t care don?t care 0 1 3 don?t care don?t care 1 0 7 don?t care don?t care 1 1 15 table 19. arming count limit definitions (count mode) aws_yn[1] aws_yn[0] aws_yp[1] aws_y p[0] y-axis sample count limit don?t care don?t care 0 0 1 don?t care don?t care 0 1 3 don?t care don?t care 1 0 7 don?t care don?t care 1 1 15 table 20. arming threshold registers location bit a d d r e s sr e g i s t e r76543210 $10 armt_xp at_xp[7] at_xp[6] at_xp[5] at_ xp[4] at_xp[3] at_xp[2] at_xp[1] at_xp[0] $11 armt_yp at_yp[7] at_yp[6] at_yp[5] at_ yp[4] at_yp[3] at_yp[2] at_yp[1] at_yp[0] $12 armt_xn at_xn[7] at_xn[6] at_xn[5] at_xn[4] at_xn[3] at_xn[2] at_xn[1] at_xn[0] $13 armt_yn at_yn[7] at_yn[6] at_yn[5] at_yn[4] at_yn[3] at_yn[2] at_yn[1] at_yn[0] r e s e t v a l u e 00000000
sensor 20 freescale semiconductor, inc. mma65xx the values programmed into the threshold registers are the th reshold values used for the arming function as described in section 3.8.10 . the threshold registers hold independent unsigned 8-bit val ues for each axis and polarity. each threshold incre- ment is equivalent to one output lsb. ta b l e 2 1 shows examples of some threshold register values and the corresponding thresh- old. if either the positive or negative threshold for one axis is programmed to $00, comparisons are disabled for only that polarity . the arming function still operates for the opposite polarity. if both the positive and negative arming thresholds for one axis are programmed to $00, the a rming function for the associated axis is disabled, and the associated output pin is disabled, regardle ss of the value of the a_cfg bits in the devcfg register. 3.1.11 device status register (devstat) the device status register is a read-only register. a read of this register clears the status flags affected by transient condi tions. reference section 4.5 for details on the response for each status condition. 3.1.11.1 unused bits (unused) the unused bits have no impact on operation or perfo rmance. when read these bits may be ?1? or ?0?. 3.1.11.2 internal data error flag (ide) the internal data error flag is set if a customer or otp register data crc fault or other internal fault is detected as defined in section 4.5.5 . the internal data error flag is cleared by a read of th e devstat register. if the error is associated with a crc fault in the writable register array, the fault will be re-asserted and will require a device reset to clear. if the error is associa ted with the data stored in the fuse array, the fault will be re-asserted even after a device reset. 3.1.11.3 device initialization flag (devinit) the device initialization flag is set during the interval between negation of internal reset and completion of internal device ini- tialization. devinit is cleared automatically. the device initiali zation flag is not affected by a read of the devstat register . 3.1.11.4 spi miso data mism atch error flag (misoerr) the miso data mismatch flag is set when a miso data mismatch fault occurs as specified in section 4.5.2 . the misoerr flag is cleared by a read of the devstat register. 3.1.11.5 offset monitor erro r flags (off_x, offset_y) the offset monitor error flags are set if the acceleration signal of the associated axis reaches the specified offset limit. th e offset monitor error flags are cleared by a read of the devstat register. 3.1.11.6 device reset flag (devres) the device reset flag is set during device initialization following a device reset. the device reset flag is cleared by a read of the devstat register. table 21. threshold register value examples axis type programmed thresholds positive threshold (g) negative threshold (g) range (g) sensitivity (lsb/g) positive (decimal) negative (decimal) 80 24 100 50 4.17 -2.08 80 24 255 0 10.625 disabled 80 24 50 20 2.08 -0.83 80 24 150 75 6.25 -3.125 105.5 18.2 100 50 5.50 -2.75 105.5 18.2 255 0 14.0 disabled 105.5 18.2 50 20 2.75 -1.10 105.5 18.2 150 75 8.24 -4.12 table 22. device status register location bit a d d r e s sr e g i s t e r76543210 $14 devstat unused ide unused devinit misoerr off_y off_x devres
sensor freescale semiconductor, inc. 21 mma65xx 3.1.12 count register (count) the count register is a read-only register which provides the current value of a free-running 8-bit counter derived from the pr i- mary oscillator. a 10-bit pre-scaler divides the primary oscillator frequency by 1024. thus, the value in the register increase s by one count every 128 s and the counter rolls over every 32.768 ms. 3.1.13 offset correction value registers (offcorr_x, offcorr_y) the offset correction value registers are read-only registers which contain the most recent of fset correction increment / dec- rement value from the offset cancellation circuit. the values stored in these regist ers indicate the amoun t of offset correctio n be- ing applied to the spi output data. the values have a resolution of 1 lsb. 3.1.14 reserved registers (reserved) registers $1c and $1d are reserved. a write to the reserved bi ts must always be logic ?0? for normal device operation and performance. 3.2 customer accessible data array crc verification 3.2.1 otp shadow register array crc verification the otp shadow register array is verified for errors using a 3-bit crc. the crc verification uses a generator polynomial of g(x) = x 3 + x + 1, with a seed value = ?111?. if a crc error is detected in the otp array, th e ide bit is set in the devstat register. 3.2.2 writable register crc verification the writable registers in the data array are verified for errors using a 3-bit crc. the crc verification is enabled only when the endinit bit is set in the devcfg register. the crc verification uses a generator polynomial of g(x) = x 3 +x+1, with a seed value = ?111?. if a crc error is detected in the writable register array, the ide bit is set in the devstat register. table 23. count register location bit a d d r e s sr e g i s t e r76543210 $15 count count[7] count[6] count[5] count[4] count[3] count[2] count[1] count[0] r e s e t v a l u e 00000000 table 24. offset correction value register location bit a d d r e s sr e g i s t e r76543210 $16 offcorr_ x offcorr_ x[7] offcorr_ x[6] offcorr_ x[5] offcorr_ x[4] offcorr_ x[3] offcorr_ x[2] offcorr_ x[1] offcorr_ x[0] $17 offcorr_ y offcorr_ y[7] offcorr_ y[6] offcorr_ y[5] offcorr_ y[4] offcorr_ y[3] offcorr_ y[2] offcorr_ y[1] offcorr_ y[0] r e s e t v a l u e 00000000 table 25. reserved registers location bit a d d r e s sr e g i s t e r76543210 $1c reserved reserved reserved reserved reserved reserved reserved reserved reserved $1d reserved reserved reserved reserved reserved reserved reserved reserved reserved r e s e t v a l u e 00000000
sensor 22 freescale semiconductor, inc. mma65xx 3.3 voltage regulators separate internal voltage regulators supply the analog and digital circuitry. external filter capacitors are required, as shown in figure 1 . the voltage regulator module includes voltage monitoring circuitry which indicates a device reset until the external sup- ply and all internal regulated voltages are within predetermined limits. a reference generator provides a stable voltage which is used by the ? converters. figure 8. power supply block diagram figure 9. voltage monitoring v rega v reg v cc tracking regulator voltage regulator reference generator v rega = 2.50 v digital logic dsp otp array primary oscillator ? converter bias generator trim trim v ref = 1.250 v v reg = 2.50 v bandgap reference tracks v rega set devres flag v cc v rega v reg v ref monitor bandgap v ccuv v regov v reguv v regauv v regaov v refov v refuv ground loss monitor v reg por v bgmon v porref note: no external access to reference voltage limits verified by characterization only
sensor freescale semiconductor, inc. 23 mma65xx 3.3.1 c vreg failure detection the digital supply voltage regulator is designed to be unstable with low capacitance. if the connection to the v reg capacitor becomes open, the digital supply voltage will oscillate and cause either an under voltage, or over voltage failure within one i nter- nal sample time. this failure will result in one of the following: 1. the devres flag in the devstat register will be set. the device will respond to spi acceleration requests as defined in ta b l e 3 0 . 2. the device will be held in reset and be non-responsive to spi requests. 3.3.2 c vrega failure detection the analog supply voltage regulator is designed to be uns table with low capacitance. if the connection to the v rega capacitor becomes open, the analog supply voltage will oscillate and caus e either an under voltage, or ov er voltage failure within one in - ternal sample time. the devres flag in the devstat register will be set. the device will respond to spi acceleration requests as defined in ta b l e 3 0 . 3.3.3 v ss and v ssa ground loss monitor the device detects the loss of ground connection to either v ss or v ssa . a loss of ground connection to v ss will result in a v reg overvoltage failure. a loss of ground connection to v ssa will result in a v reg undervoltage failure. both failures result in a device reset. 3.3.4 spi initiated reset in addition to voltage monitoring, a device re set can be initiated by a specific series of three write operations involving the res_1 and res_0 bits in the devctl register. reference section 3.1.5.1 . for details regarding the spi initiated reset. 3.4 internal oscillator the device includes a factory trimmed oscillator as specified in section 2.7 . 3.4.1 oscillator monitor the count register in the custom er accessible array is a read-only register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. a 10-bit pre- scaler divides the primary oscillator by 1024. thus, the value in the count register increases by one count every 128 s, and the register rolls over every 32.768 ms. the spi master can period- ically read the count register, and verify the difference between subsequent register reads against the system time base. 1. the spi access rates and deviations must be taken in to account for this oscillator verification method. 3.4.2 crc based clock monitor the device includes unique dsp cores for the x-axis and y-axis . each dsp core uses multiple frequencies derived from the oscillator, ranging from the base oscillator frequency to the base oscillator frequency divided by 256. in order to guarantee t hat the clocks for the two dsp cores are synchronized, a clock cr c monitor is employed. the crc monitor is updated every cycle of the base oscillator. 3.5 transducer the transducer is an overdamped mass-spring-damper s ystem described by the following transfer function: where: = damping ratio n = natural frequency = 2 ?? f n reference section 2.4 for transducer parameters. hs () n 2 s 2 2 n s ?? ? n 2 ++ ------------------------------------------------------ =
sensor 24 freescale semiconductor, inc. mma65xx 3.6 self test interface when self test is enabled, the self test interface applies a voltage to the g-cell, c ausing a deflection of the proof mass. onc e enabled, offset cancellation is suspended and the deflection results in an acceleration which is superimposed upon the input ac - celeration. the resulting acceleration readings can be compared either against absolute limits, or the values stored in the self test de- flection registers (reference section 3.1.2 ). the self test interface is controlled th rough spi write operatio ns to the devcfg_x and devcfg_y registers described in section 3.1.7 only if the endinit bit in the devcfg register is cleared. a diagram of the self test interface is shown in figure 10 . figure 10. self test interface 3.6.1 raw self test deflection verification the raw self test deflection can be directly ve rified against raw self test limits listed in section 2.4 . 3.6.2 delta self test deflection verification the raw self test deflection can be verified against the ambient temperature self test deflection value recorded at the time th e device was produced. the production self te st deflection is stored in the stdefl_x and stddefl_y registers such that the minimum stored value (0x00) is equivalent to st min , and the maximum stored value (0xff) is equivalent to st max . the delta self test deflection limits can then be determined by the following equations: where: y-axis g-cell self test voltage generator endinit st_y st_x x-axis g-cell endinit endinit st acc the accuracy of the self test deflection relative to the stored deflection as specified in section 2.4 . stdeflx cnts the value stored in the stdefl_x or stdefl_y register. st min the minimum self test deflection at 25c as specified in section 2.4 . st max the maximum self test deflection at 25c as specified in section 2.4 . st accminlimit floor st min stdeflx cnts 255 ------------------------------------------ st max st min ? [] + ?? ?? 1 st acc ? () ? = st accmaxlimit ceil st min stdeflx cnts 255 ------------------------------------------ st max st min ? [] + ?? ?? 1 st acc + () ? =
sensor freescale semiconductor, inc. 25 mma65xx 3.7 ? converter a sigma delta converter provides the interface betwe en the transducer and the dsp. the output of the ? converter is a data stream at a nominal frequency of 1 mhz. figure 11. ? converter block diagram 3.8 digital signal processing block a digital signal processing (dsp) block is used to perform si gnal filtering and compensation op erations. a diagram illustrating the signal processing flow is shown in figure 12 . figure 12. signal chain diagram 1-bit quantizer z -1 1 - z -1 z -1 1 - z -1 first integrator second integrator 1 = 1 2 2 v x c int1 g-cell c bot c top c = c top - c bot ? _out v = 2 v ref adc dac v = c x v x / c int1 ? _out to spi to arm_x a b c eg to spi h i df sinc filter section 3.8.2 low pass filter section 3.8.3 compensation section 3.8.6 interpolation section 3.8.7 offset cancellation section 3.8.4 offset cancellation output scaling raw output scaling arm/pcm output section 3.8.9 section 3.8.10 table 26. signal chain characteristics description sample time ( s) data width bits over range bits effective bits rounding resolution bits typical block latency reference asd 1 1 1 3.2 s section 3.7 b sinc filter 8 14 13 11.2 s section 3.8.2 c low pass filter 8/16 20 4 12 4 reference section 3.8.3 section 3.8.3 d compensation 8/16 20 4 12 4 7.875 s section 3.8.6 e interpolation 4/8 20 4 12 4 t s / 2 section 3.8.8 f offset cancellation 256 20 4 12 4 n/a section 3.8.4 gh spi output 4/8 ? ? 12 ? t s / 2 i pcm output 4/8 ? ? 9 ? section 3.8.11
sensor 26 freescale semiconductor, inc. mma65xx 3.8.1 dsp clock the dsp is clocked at 8 mhz, with an effe ctive 6mhz operating frequency. the clock to the dsp is disabled for 1 clock prior to each edge of the ? modulator clock to minimize noise during data conversion. figure 13. clock generation 3.8.2 decimation sinc filter the serial data stream produced by the ? converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 8 or 16, depending on the low pass filter selected. figure 14. sinc filter response, t s = 8 s 3.8.3 low pass filter data from the sinc filter is processed by an infinite impulse response (iir) low pass filter. . the device provides the option for one of twelve low-pass filters. the filter is selected independently for each axis with the lpf_x[3:0] and lpf_y[3:0] bits in the devcfg_x and devcfg _y registers. the filter sele ction options are listed in section 3.1.7.3 , ta b l e 11 . response parameters for the lo w-pass filter are specified in section 2.4 . filter characteristics are illus- trated in the figures on the following pages. 8 mhz osc 6 mhz digital 1mhz modulator hz () 1 z 16? ? 16 1 z 1? ? () ---------------------------------- - 3 = hz () n 0 n 1 z 1? ? () n 2 z 2? ? () n 3 z 3? ? () n 4 z 4? ? () ++++ d 0 d 1 z 1? ? () d 2 z 2? ? () d 3 z 3? ? () d 4 z 4? ? () ++++ ------------------- ------------------------------------------------------------------------------------------------------------ -- =
sensor freescale semiconductor, inc. 27 mma65xx note: low pass filter figures do not include g-cell frequency response. table 27. low pass filter coefficients filter number lpf_x/ lpf_y value (hex) description -3db frequency (5%) filter order sample time ( s 5%) filter coefficients group delay self test step response (ms) 8 0x08 50 hz lpf 4 16 n 0 2.08729034056887e-10 d 0 1 26816/ f osc 14.00 n 1 8.349134489240434e-10 d 1 -3.976249694824219 n 2 1.25237777794924e-09 d 2 5.929003009577855 0 0x00 100 hz lpf 4 8 n 3 8.349103355433541e-10 d 3 -3.929255528257727 7.00 n 4 2.087307211059861e-10 d 4 0.9765022168437554 9 0x09 150 hz lpf 4 16 n 0 1.639127731323242e-08 d 0 1 9024/ f osc 6.00 n 1 6.556510925292969e-08 d 1 -3.928921222686768 n 2 9.834768482194806e-08 d 2 5.789028996785419 1 0x01 300 hz lpf 4 8 n 3 6.556510372902331e-08 d 3 -3.791257019240902 3.00 n 4 1.639128257923422e-08 d 4 0.9311495074496179 10 0x0a 200 hz lpf 4 16 n 0 5.124509334564209e-08 d 0 1 6784/ f osc 5.00 n 1 2.049803733825684e-07 d 1 -3.905343055725098 n 2 3.074705789151505e-07 d 2 5.72004239520561 2 0x02 400 hz lpf 4 8 n 3 2.049803958150164e-07 d 3 -3.723967810019985 2.50 n 4 5.124510693742625e-08 d 4 0.9092692903507213 13 0x0d 200 hz lpf 3 16 n 0 2.720393240451813e-06 d 0 1 5632/ f osc 4.80 n 1 8.161179721355438e-06 d 1 -2.931681632995605 n 2 8.161180123840722e-06 d 2 2.865296718275204 5 0x05 400 hz lpf 3 8 n 3 2.720393634345496e-06 d 3 -0.9335933215174919 2.40 n 4 0d 4 0 11 0x0b 400 hz lpf 4 16 n 0 7.822513580322266e-07 d 0 1 3392/ f osc 2.50 n 1 3.129005432128906e-06 d 1 -3.811614513397217 n 2 4.693508163398543e-06 d 2 5.450666051045118 3 0x03 800 hz lpf 4 8 n 3 3.129005428784364e-06 d 3 -3.465805771100349 1.70 n 4 7.822513604678875e-07 d 4 0.8267667478030489 12 0x0c 500 hz lpf 4 16 n 0 1.865386962890625e-06 d 0 1 2688/ f osc 3.20 n 1 7.4615478515625e-06 d 1 -3.765105724334717 n 2 1.119232176112846e-05 d 2 5.319861050818872 4 0x04 1000 hz lpf 4 8 n 3 7.4615478515625e-06 d 3 -3.34309015036024 1.60 n 4 1.865386966264658e-06 d 4 0.7883646729233078
sensor 28 freescale semiconductor, inc. mma65xx figure 15. low-pass filter characteristics: f c = 100 hz, poles = 4, t s = 8 s
sensor freescale semiconductor, inc. 29 mma65xx figure 16. low-pass filter characteristics: f c = 300 hz, poles = 4, t s = 8 s
sensor 30 freescale semiconductor, inc. mma65xx figure 17. low-pass filter characteristics: f c = 400 hz, poles = 4, t s = 8 s
sensor freescale semiconductor, inc. 31 mma65xx figure 18. low-pass filter characteristics: f c = 400 hz, poles = 3, t s = 8 s
sensor 32 freescale semiconductor, inc. mma65xx figure 19. low-pass filter characteristics: f c = 800 hz, poles = 4, t s = 8 s
sensor freescale semiconductor, inc. 33 mma65xx figure 20. low-pass filter characteristics: f c = 1000 hz, poles = 4, t s = 8 s
sensor 34 freescale semiconductor, inc. mma65xx 3.8.4 offset cancellation the device provides the option to read offset cancelled a cceleration data via the spi by clearing the oc bit in the devcfg register (reference section 3.1.6.1 ) and in the spi command (reference section 4.1 ). a block diagram of the offset cancellation is shown in figure 21 , and response parameters are specified in section 2.4 and in ta b l e 2 8 . figure 21. offset cancellation block diagram in normal operation, the offset cancellati on circuit computes a 24,576 sample running average of the acceleration data down- sampled to 256 s. the running average is compared agai nst positive and negative thresholds to determine the offset correction value that will be applied to the acceleration data. during start up, three phases of moving average sizes are used to allow for faster convergenc e of misuse input signals. ref- erence ta b l e 2 8 for offset cancellation timing information during startup and normal operation. the offset cancellation startup phase can also be directly cont rolled during initialization (endinit = ?0?) using the ocphase[1:0] bits and the offcfg_en bit in the devctl register, as described in section 3.1.5.2 and section 3.1.5.3 . when the self test circuitry is active, the offset cancellati on block and the offset monitor block are suspended, and the offse t correction value is constant. once the self test circuitry is disabled, the offset cancellation block remains suspended for the time t st_omb to allow the acceleration output to return to it?s nominal offset. 3.8.5 offset monitor the device provides the option for an offset monitor circuit. the offset monitor circuit is enabled when the ofmon bit in the devcfg register is programmed to a logic ?1 ?. the output of the offset cancellation circuit is compared against a high and low threshold. if the offset correction value exceeds either the offthr pos , or offthr neg threshold, an offset over range error condition is indicated. the offset correction value update rate is listed in ta b l e 2 8 : ?maximum slew rate?. because the offset monitor uses this value, the offset monitor will also update at this rate. the time to indicate an offset over range error is dependent upon the input s ignal. the offset monitor status remains suspended during self test, be cause the offset monitor is ba sed on the offset cancellation circuit, which is also suspended during self test. the offset m onitor is disabled for 2.1 seconds following reset regardless of the state of the ofmon bit. table 28. offset cancellati on timing specifications phase start time of phase (from por) typical time in phase (ms) # of samples in phase samples averaged off_corr_value update rate (ms) averaging period (ms) maximum slew rate (lsb/s) averaging filter -3db frequency (hz) start 1 t op 524.288 2048 48 2.048 12.288 122.1 36.05 start 2 t op + 524.288 524.288 2048 384 16.38 98.304 15.26 4.506 start 3 t op + 1048.576 524.288 2048 3072 131.1 786.432 1.907 0.5632 normal t op + 1572.864 ? ? 24576 1049 6291.456 0.2384 0.07040 accumulator t1 4096 samples shift lpf out t2 t5 t4 t3 t6 offset inc/dec off corrp off corrn 1/8 lsb 1/8 lsb increment 1/4 lsb downsampled to 256 s off_corr_value offthr neg offthr pos off_err off_err alignment correction 1.049s t registers updated every 1.049s decrement 1/4 lsb 6.291s average updated every 1.049s oc out
sensor freescale semiconductor, inc. 35 mma65xx 3.8.6 signal compensation the device includes internal otp and signal processing to compen sate for sensitivity error and offset error. this compensation is necessary to achieve the specified parameters in section 2.4 . 3.8.7 output scaling the 20 bit digital output from the dsp is clipped and scaled to a 12-bit data word which spans the acceleration range of the device. figure 22 shows the method used to establish the output acceleration data word from the dsp output. figure 22. 12-bit output scaling diagram 3.8.8 data interpolation the device includes 2 to 1 data interpolation to minimize the sy stem sample jitter. each result produced by the digital signal processing chain is delayed one half of a sample time, and t he interpolated value of successive samples is provided between sample times. this operation is illustrated below. figure 23. data interpolation timing over range signal noise d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 12-bit data word d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 using rounding s n-3 s n-2 t t internal sample rate output sample rate s n-1 t s t s s n-1 t s s n s n-2 s n 3? s n 2? + 2 ------------------------------- s n 2? s n 1? + 2 ------------------------------- s n 1? s n + 2 ------------------------ s n-3 spi acceleration request occurring in this window receives interpolated sample spi acceleration request occurring in this window receives true sample.
sensor 36 freescale semiconductor, inc. mma65xx the effect of this interpolat ion at the system level is a 50% reduction in sample jitter. figure 24 shows the resulting output data for an input signal. figure 24. data interpolation example 3.8.9 acceleration data timing the spi uses a request/response protocol , where a spi transfer is completed thro ugh a sequence of 2 phases. reference section 4 for more details regarding the spi protocol. the device latc hes the associated data for an acceleration request at the rising edge of cs . the most recent sample available from the dsp (inclu ding interpolation) is latched, and transmitted during the subsequent spi transfer. figure 25. acceleration data timing 40 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 time counts input signal internally sampled signal interpolated samples internally sampled values earliest transmission point of interpolated values earliest transmission point of internally sampled values window of transmission for sampled values (maximum: t s / 2) window of transmission for interpolated values (maximum: t s / 2) fixed latency: t s / 2 = signal jitter = sclk mosi miso cs request x-axis request y-axis x-axis response y-axis response request x-axis request y-axis x-axis response x-axis data latched y-axis data latched x-axis arm function updated y-axis arm function updated if applicable
sensor freescale semiconductor, inc. 37 mma65xx 3.8.10 arming function the device provides the option for an arming function with 3 m odes of operation. the operation of the arming function is se- lected by the state of the a_cf g bits in the devcfg register. reference section 4.5 for the operation of the arming function with exc eption conditions. error conditions do not impact prior arming function responses. if an error occurs after an arming ac tivation, the corresponding pulse stretch for the existing armi ng condition will continue. however, new acceleration reads will not update the arming function regardless of the acceleration val ue. 3.8.10.1 arming function: moving average mode in moving average mode, the arming function runs a moving av erage on the offset cancelled out put of each acceleration axis. the number of samples used for the moving average (k) is programmable via the aws_xx[1:0 ] and arm_yx[1:0] bits in the armcfgx and armcfgy re gisters. reference section 3.1.8 for register details. arm_ma n = (oc n + oc n-1 + ... + oc n+1-k )/k where n is the current sample. the sample rate for each axis is determined by the spi acceleration data sample rate. at the rising edge of cs for an accel- eration data spi request, the moving average for the as sociated axis is updated with a new sample. reference figure 28 . the spi acceleration data sample rate must meet the minimum time between requests (t acc_req_x ) specified in section 2.6 . the moving average output is compared against positive and negative 8-bit thresholds that are individually programmed for each axis via the armt_xx and armt_yx registers. reference section 3.1.10 for register details. if the moving average equals or exceeds either threshold, an arming condition is indicated, the arm_x or arm_y output is asserted for the associated axis, and the pulse stretch counter is set as described in section 3.8.10.4 . the arm_x or arm_y output is de-asserted only when the pulse stretch counter expires. figure 28 shows the arming output operation for different spi conditions. figure 26. arming function block diagram - moving average mode the moving average window size must be set prior to setting the arming function to moving average mode, or prior to request- ing acceleration data via the spi. if the moving average window size is changed after enabling moving average mode, the arming function must first be disabled by setting the a_cfg bits to ?000 ?. once the desired moving average window size is set, the mov - ing average mode can be re-enabled. offset cancellation aws_xp[1:0] aps_x[1:0] pulse stretch arm_x gating i/o armt_xn[7:0] armt_xp[7:0] moving average positive moving average negative aws_xn[1:0] offcanc_arm_x[10:0]
sensor 38 freescale semiconductor, inc. mma65xx 3.8.10.2 arming function: count mode in count mode, the arming function compares each offset cancelled sample against positive and negative thresholds that are individually programmed for each axis via th e armt_xx and armt_yx registers. reference section 3.1.10 for register details. if the sample equals or exceeds either thre shold, a sample counter is incremented. if the sample does not exceed either thresh- old, the sample counter is reset to zero. the sample rate for each axis is determined by the spi acceleration data sample rate. at the rising edge of cs for an accel- eration data spi request, a new sample for the associat ed axis is compared against the thresholds. reference figure 28 . the spi acceleration data sample rate must meet the minimum time between requests (t acc_req_x ) specified in section 2.6 . a sample count limit is programmable via the aws_xx[1:0] and aws_yx[1:0] bits in the armcfgx and armcfgy registers. if the sample count reaches the programmable sample count limit, an arming condition is indicated, the arm_x or arm_y output is asserted for the associated axis, and the pulse stretch counter is set as described in section 3.8.10.4 . the arm_x or arm_y output is de-asserted only when the pulse stretch counter expires. figure 28 shows the arming output operation for different spi conditions. figure 27. arming function block diagram - count mode figure 28. x and y axis arming conditions, moving average and count mode armt_xn[7:0] offset cancellation aws_xp[1:0] aps_x[1:0] pulse stretch arm_x armt_xp[7:0] gating i/o 1-4 sample counter offcanc_arm_x[10:0] y-axis arm condition present sclk mosi miso cs request x-axis request y-axis x-axis response y-axis response request x-axis request y-axis x-axis response arm_x arm_y y-axis response y-axis arm condition not present x-axis arm condition not present x-axis arm condition present y- axi s da ta latched for t arm y-axis pulse stretch x-axis pulse stretch arm & spi x-axis data latched for arm & spi x-axis data latched for arm & spi
sensor freescale semiconductor, inc. 39 mma65xx 3.8.10.3 arming functi on: unfiltered mode on the rising edge of cs for an acceleration request, the most recent availa ble offset cancelled sample for the requested axis is compared against positive and negative thresholds that are individually programmed for each axis via the armt_xx and armt_yx registers. reference section 3.1.10 for register details. if the sample equals or exceeds either threshold, an arming condition is indicated. once an arming condition is indicated for the x-axis, the arm_x output is asserted when cs is asserted and the miso data includes an acceleration response for that axis. once an arming condition is indicated for the y-axis, the arm_y output is asserted when cs is asserted and the miso data includes an acceleration response for that axis. the pulse stretch function is not applied in unfiltered mode. figure 29 contains a block diagram of the arming function operation in unfiltered mode. figure 30 shows the arming output operation under the different spi request conditions. figure 29. arming function block diagram - unfiltered mode figure 30. x and y axis arming conditions, unfiltered mode arming function acfg[2] cs axis select interpolated sample rate arm_x i/o acfg[1] y-axis arm condition present sclk mosi miso cs request x-axis request y-axis x-axis response y-axis response request x-axis request y-axis x-axis response arm_x arm_y y-axis response y-axis arm condition not present x-axis arm condition not present x-axis arm condition present t arm_uf_dly t arm_uf_assert t arm_uf_dly t arm_uf_assert x-axis data latched for arm & spi y- axi s da ta latched for arm & spi x-axis data latched for arm & spi
sensor 40 freescale semiconductor, inc. mma65xx 3.8.10.4 arming pulse stretch function a pulse stretch function can be applied to the arming outputs in moving average mode, or count mode. if the pulse stretch function is not used (aps_x[1:0] = ?00? or aps_y[1:0] = ?00?), the arming ou tput is asserted if and only i f an arming condition exists for the associated axis after the most recent evaluated sample. the arming output is de-asserted if and only if an arming condition does not exist for the associated axis after the most recent evaluated sample. if the pulse stretch function is used, ( aps_x[1:0] not equal ?00? or aps_y[1:0] not equal ?00?), the arming output is controlle d only by the value of the pulse stretch timer value. if the puls e stretch timer value is non-zero, the arming output is asserted . if the pulse stretch timer is zero, the arming output is de-asserted. the pulse stretch counter continuously decrements until it reach es zero. the pulse stretch counter is reset to the programmed pulse stretch value if and only if an arming condition exists for th e associated axis after the most recent evaluated sample. reference figure 28 . the desired pulse stretch time is individually programmable for each axis via the aps_x[1:0] and aps_y[1:0] bits in the arm- cfg register. exception conditions listed in section 4.5 do not impact prior arming function response s. if an exception occurs after an arming activation, the corresponding pulse stretch for the existing arming condition will continue. however, new acceleration reads wi ll not reset the pulse stretch counter regardless of the acceleration value. 3.8.10.5 arming pin output structure the arming output pin structure can be set to active high, or active low with the a_cfg bits in the devcfg register as de- scribed in section 3.1.6.6 . the active high and active low pin output structures are shown in figure 31 . figure 31. arming function - pin output structure arm function arm_x gating v cc arm function arm_x gating v cc open drain, active high open drain, active low
sensor freescale semiconductor, inc. 41 mma65xx 3.8.11 pcm output function the device provides the option for a pcm output function. the pcm output is enabled by setting the a_cfg bits in the devcfg register to the appropr iate state as described in section 3.1.6.6 . selecting the pcm output ena bles the following func- tions: ? the pcm_x and pcm_y pins are programmed as a digital outputs. reference section 2.3 for the pin electrical parameters. ? the acceleration value output from the offset cancellation bl ock is saturated to 9-bits and converted to an unsigned value. note, the 9-bit unsigned acceleration value us es the full range of values (0 - 511). ? the 9-bit acceleration value is input into a summer clocked at 8mhz. ? the carry from the summer circuit is output to the pcm pin. a block diagram of the pcm output is shown in figure 32 . exception conditions affect the pcm output as listed in section 4.5 . figure 32. pcm output function block diagram output scaling oc_x[9:1] a 9 bit adder arm_x/pcm_x b carry sum f clk = 8 mhz sample updated every 8 s 9 9 9 d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q
sensor 42 freescale semiconductor, inc. mma65xx 3.9 serial peripheral interface the device includes a serial peripheral interface (spi) to prov ide access to the configuration registers and digital data. ref- erence section 4 for details regarding the spi protocol and available commands. to maximize independence between the x and y channels, the device includes two interface blocks, one for each axis. the x-axis interface block responds only to x-axis acceleration requ ests, or even addressed register commands. the y-axis interface block responds only to y-axis acceleration requests, or odd ad dressed register commands. to the spi master, the device oper- ates as a single device. the internal independent blocks are transparent. each spi block has an independent shift register. once a message is received (rising edge of cs ), the contents of the two shift registers are compared. if the contents do not match, the y-axis spi block will not respond, and the x-axis spi block wil l respond with a spi error as shown in table 30 . if the contents match, each spi block decodes the message, and the appropriate block enables do for a response during the next spi message. figure 33 shows an internal diagram of the spi. figure 33. spi diagram y spi cs_m sclkm mosim i/o misom cs sclk mosi miso cs sclk mosi miso spi master x spi if bit 13 == ?1? if bit 13 = ?0? & bit 14 == ?1? & a0 == ?1? if bit 13 == ?1? if bit 13 = ?0? & bit 14 == ?0? & a0 == ?0? registers x-axis raw data x-axis oc data even address regs y-axis raw data y-axis oc data odd address regs x spi shift register y spi shift register spi mismatch error (spi error)
sensor freescale semiconductor, inc. 43 mma65xx 3.10 device initialization following power-up, under-voltage reset, or a spi reset comman d sequence, the device proceeds through an internal initial- ization process as shown below. figure 34 also shows the device performance for an example external system level initialization procedure. figure 34. initialization process dly por otp copy to mirror registers offset cancellation startup phase 2 initialize r/w registers to desired state verify x-axis offset verify x-axis self test & arm_x asserted verify y-axis offset & arm_y deasserted verify x-axis offset & arm_x deasserted verify y-axis self test & arm_y asserted verify x-axis offset & arm_x deasserted verify y-axis offset & arm_y deasserted offset cancellation startup phase 1 offset cancellation startup phase 3 offset cancellation normal mode ready for spi command endinit clear dly dly dly re-initialize r/w registers (if needed) activate x-axis self test internal offset error corrected to ?0? deactivate x-axis self test activate y-axis self test deactivate y-axis self test normal mode internal initialization external initialization delay deassertion dependent on pulse stretch and/or arming mode deassertion dependent on pulse stretch and/or arming mode assertion dependent on arming mode assertion dependent on arming mode set endinit read devstat to clear flags re-read devstat to verify status t st_omb t oc_phase1 t oc_phase2 t oc_phase3 t op and x_st y_st x_arm y_arm notes:1) x-axis and y-axis self test can be enabl ed and evaluated simultaneously to reduce test time. for failure mode coverage of the arming pins and of potential common axis failures, freescale recommends independent self test activation. t strise 2) t strise and t stfall are dependent on the selected lpf group delay. t stfall
sensor 44 freescale semiconductor, inc. mma65xx 3.11 overload response 3.11.1 overload performance the device is designed to operate within a specified range. acceleration beyond that range (overload) impacts the output of the sensor. acceleration beyond the range of the device can generate a dc shift at the output of the device that is dependent upon the overload frequency and amplitude. the g-cell is over damped, providing the optimal desig n for overload performance. however, the performance of the device during an overload co ndition is affected by many other parameters, including: ? g-cell damping ?non-linearity ? clipping limits ? symmetry figure 35 shows the g-cell, adc and output clipping of the device ov er frequency. the relevant parameters are specified in section 2.1 , and section 2.7 . figure 35. output clipping vs. frequency 3.11.2 sigma delta over range response over range conditions exist when the signal level is beyond th e full-scale range of the device but within the computational lim its of the dsp. the ? converter can saturate at levels above those specified in section 2.1 (g adc_clip ). the dsp operates pre- dictably under all cases of over range, al though the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. 5khz f g-cell f lpf g adc_clip g g-cell_clip determined by g-cell 10khz g-cell rolloff acceleration (g) frequency (khz) lpf rolloff r e g i o n c l i p p e d b y g - c e l l r e g i o n c l i p p e d b y a d c r e g i o n o f s i g n a l d i s t o r t i o n d u e t o a s y m m e t r y a n d n o n - l i n e a r i t y region of no signal distortion beyond specification region of interest roll-off and adc clipping g range_norm determined by g-cell roll-off and full scale range region clipped by output
sensor freescale semiconductor, inc. 45 mma65xx 4 spi communications communication with the device is completed through synchronous serial transfers via spi. the device is a slave device con- figured for cpol = 0, cpha = 0, msb first. spi transfers ar e completed through a sequence of two phases. during the first phase, the type of transfer and associated control information is transmitted from the spi master to the device. data from the device is transmitted during the second phase. any activity on mosi or sclk is ignored when cs is negated. consequently, intermediate transfers involving other spi devices may occur between phase one and phase two. reference figure 36 . figure 36. spi transfer detail t3p1 sclk mosi miso cs t1p1 t2p1 t1p2 t2p2 t3p2 sclk mosi miso cs phase one: command phase two: response phase one: response -previous command
sensor 46 freescale semiconductor, inc. mma65xx 4.1 spi command format commands are transferred from the spi master to the device. valid commands fall into two categories: register operations, and acceleration data requests. table 29. spi command message summary msb lsb 1514131211109876543210 0 ax a oc 0 0 0 0 0 0 0 0 1 sd arm p command type reference ax= axis selection 0 x-axis acceleration data 1 y-axis acceleration data a = acceleration data request 0 register operation 1 acceleration data request oc = offset cancelled data confirmation 0 offset cancelled data enabled 1 raw acceleration data enabled sd = signed data confirmation signed data enabled 0 unsigned data enabled 1 arm = arm function status confirmation disabled / pcm output enabled 0 arming function enabled 1 p = odd parity 0 ax a oc 0 0 0 0 0 0 0 0 0 sd arm p accel data 0010000000001001 x-axis oc, signed, disabled/pcm 0010000000001010 x-axis oc, signed, arm enabled 0010000000001100 x-axis oc, unsigned, disabled/pcm 0010000000001111 x-axis oc, unsigned, arm enabled 0011000000001000 x-axis raw, signed, disabled/pcm 0011000000001011 x-axis raw, signed, arm enabled 0011000000001101 x-axis raw, unsigned, disabled/pcm 0011000000001110 x-axis raw, unsigned, arm enabled 0110000000001000 y-axis oc, signed, disabled/pcm 0110000000001011 y-axis oc, signed, arm enabled 0110000000001101 y-axis oc, unsigned, disabled/pcm 0110000000001110 y-axis oc, unsigned, arm enabled 0111000000001001 y-axis raw, signed, disabled/pcm 0111000000001010 y-axis raw, signed, arm enabled 0111000000001100 y-axis raw, unsigned, disabled/pcm 0111000000001111 y-axis raw, unsigned, arm enabled p ax a d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command type reference p00 a4 a3 a2 a1 a0 00000000 register read section 4.4 register address p10 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 register write section 4.4 register address data to be written to register p = odd parity
sensor freescale semiconductor, inc. 47 mma65xx 4.2 spi response format table 30. spi response message summary msb lsb 1514131211109876543210 cmd a ax response to valid acceleration request reference d15 d14 ax p d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 acceleration d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 ax = axis requested 0 x-axis acceleration response 1 y-axis acceleration response p = odd parity s[1:0] = device status 0 0 in initialization (endinit = ?0?) 0 1 normal request 10 st active 1 1 internal error present / spi error cmd a ax d1 d0 ax p s1 s0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 reference valid accel request 1 0 accel data 0 p 0 1 x- axis acceleration data section 4.3 1 0 accel data 0 p 1 0 x- axis self test active acceleration data 1 0 accel data 0 p 0 0 x- axis acceleration data, initialization in process (endinit=?0?) 1 1 accel data 1 p 0 1 y-axis acceleration data 1 1 accel data 1 p 1 0 y-axis self test active acceleration data 1 1 accel data 1 p 0 0 y- axis acceleration data, initialization in process (endinit=?0?) msb lsb 1514131211109876543210 cmd a ax response to valid register access reference d15 d14 ax p d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register write 01001p 1110 d7 d6 d5 d4 d3 d2 d1 d0 section 4.4.1 new contents of register register read 00010p 1110 d7 d6 d5 d4 d3 d2 d1 d0 section 4.4.2 contents of register msb lsb 1514131211109876543210 cmd a ax error responses reference d15 d14 ax p d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 invalid accel request xx 0 0axp110000000000 section 4.3 internal error present xx section 4.5.5 miso error xx 0 0 0p110000000000 section 4.5.2 spi error xx section 4.5.1 invalid register request 0x 0 0 00111000000000 section 4.4 self test error 0x 0 0axp110000000000 section 4.5.5
sensor 48 freescale semiconductor, inc. mma65xx 4.3 acceleration data transfers twelve bit acceleration data requests are initiated when the a cceleration bit of the spi command message (a) is set to a logic ?1?, and bit d[3] of the spi command message is set to a logic ?1?. the axis selection bit (ax) selects the type of acceleratio n data requested, as shown in table 31 . to verify that the device is configured as expected, each a cceleration data request includes the configuration information whic h impacts the output data. the requested conf iguration is compared against the data progr ammed in the writable register block. details are shown in table 32 . if the data listed in table 32 does not does not match, an acceleration data request mismatch failure is detected and no ac- celeration data is transmitted. reference section 4.5.3.1 . acceleration data request commands include a parity bit (p). odd parity is employed. the number of logic ?1? bits in the accel- eration data request command must be an odd number. acceleration data is transmitted on the next spi message if and only if all of the following conditions are met: ? the devinit bit in the d evstat register is not set ? the devres bit in the devst at register is not set ? the ide bit in the devstat re gister is not set (reference section 4.5.5 ) ? no spi error is detected (reference section 4.5.1 ) ? no miso error is detected (reference section 4.5.2 ) ? no acceleration data request mismatch failure is detected (reference section 4.5.3.1 ) ? no self test error is present (reference section 4.5.5.2 ) ? no offset monitor error is present for the requested channel (reference section 4.5.6 ) if the above conditions are met, the device responds with a ?valid acceleration data request? response as shown in ta b l e 3 0 . otherwise, the device responds as specified in section 4.5 . table 31. acceleration data request axis selection bit (ax) data type 0 x-axis acceleration data 1 y-axis acceleration data table 32. acceleration data re quest configuration information programmable option command message bit writable register information raw or offset cancelled data oc devcfg[7] (oc ) signed or unsigned data sd devcfg[4] (sd ) arming function or pcm output arm devcfg[2] || devcfg[1] (a_cfg[2] || a_cfg[1])
sensor freescale semiconductor, inc. 49 mma65xx 4.4 register access operations two types of register access operations are supported; register write, and register read. register access operations are initi- ated when the acceleration bit (a) of the command message is se t to a logic ?0?. the operation to be performed is indicated by the access selection bit (ax) of the command message. register access operations include a parity bit (p). odd parity is employed. the number of logic ?1 ? bits in the register acces s operation must be an odd number. 4.4.1 register write request during a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to b e written. writable registers are defined in ta b l e 3 . the response to a register write operation is shown in ta b l e 3 0 . the response is transmitted on the next spi message if and only if all of the following conditions are met: ? no spi error is detected (reference section 4.5.1 ) ? no miso error is detected (reference section 4.5.2 ) ? the endinit bit is cleared (reference section 3.1.6.3 ) ? this applies to all registers with the exception of the devctl register (only bits 6 and 7 can be modified) ? no invalid register request is detected (reference section 4.5.3.2 ) if the above conditions are met, the device responds to the register write request as shown in table 30 . otherwise, the device responds as specified in section 4.5 . register write operations do not occur in ternally until the transfer during which they are requested has been completed. in the event that a spi error is detected during a register write transfer, the write operation is not completed. 4.4.2 register read request during a register read request, bits 12 through 8 contain the fi ve-bit address for the register to be read. bits 7 through 0 mu st be logic ?0?. readable registers are defined in ta b l e 3 . the response to a register read operation is shown in ta b l e 3 0 . the response is transmitted on the next spi message if and only if all of the following conditions are met: ? no spi error is detected (reference section 4.5.1 ) ? no miso error is detected (reference section 4.5.2 ) ? no invalid register request is detected (reference section 4.5.3.2 ) if the above conditions are met, the device resp onds to the register read request as shown in table 30 . otherwise, the device responds as specified in section 4.5 . access selection bit (ax) operation 0 register read 1 register write
sensor 50 freescale semiconductor, inc. mma65xx 4.5 exception handling the following sections describe the conditions and the device re sponse for each detectable exception. in the event that mul- tiple exceptions exist, the exception response is determined by the priority listed in ta b l e 3 3 . 4.5.1 spi error the following spi conditions result in a spi error: ? sclk is high when cs is asserted ? the number of sclk risi ng edges detected while cs is asserted is not equal to 16 ? sclk is high when cs is negated ? command message parity error (mosi) ? bit 15 of acceleration data request is not equal to ?0? ? bits 4 through 11 of an acceleration request are not equal to ?0? ? bits 3 of an acceleration request is not equal to ?1? ? bits 0 through 7 of a register read request are not equal to ?0? the device responds to a spi error with a ?spi error? response as shown in table 30 . this applies to both acceleration data request spi errors, and register access spi errors. the arming function will not be updated if a spi error is detected. the pcm out put is not affected by a spi error. table 33. spi error response priority error priority exception effect on data spi data arming output pcm output 1 spi error error response no update no effect 2 spi miso error error response no update no effect 3 invalid request error response no update no effect 4 devinit bit set error response no update disabled 5 devres error error response no update disabled 6 crc error error response no update no effect 7 self test error error response no update no effect 8 offset monitor error error response no update no effect
sensor freescale semiconductor, inc. 51 mma65xx 4.5.2 spi data output verification error the device includes a function to verify the integrity of the data out put to the miso pin. the fu nction reads the data transmit ted on the miso pin and compares it against t he data intended to be transmitted. if any one bit doesn?t match, a spi miso mismatch fault is detected an d the misoerr flag in the devstat register is set. if a valid spi acceleration request message is received during the spi transfer with the miso mi smatch failure, the spi accel- eration request message is ignored and the device responds with a ?miso error? response during the subsequent spi message (reference table 30 ). the arming function is not updated if a miso mismatch failure occurs. th e pcm function is not affected by the miso mismatch failure. if a valid spi register write request message is received during t he spi transfer with the miso mismatch failure, the register write is completed as requested, but the device responds with a ?miso error? response as shown in ta b l e 3 0 , during the subse- quent spi message. if a valid spi register read request message is received during the spi transfer with the miso mismatch failure, the register read is ignored and the device responds wi th a ?miso error? response as shown in ta b l e 3 0 , during the subsequent spi mes- sage. if the register read request is for the devstat register, th e devstat register will not be cleared. in all cases, the misoerr flag in the devstat register will re main set until a successful spi register read request of the devstat register is completed. figure 37. spi data output verification 4.5.3 invalid requests 4.5.3.1 acceleration data request mismatch failure the device detects an ?acceleration data request mismatch? error if the spi ?acceleration data request? command data listed in ta b l e 3 2 does not match the internal register settings. the dev ice responds to an ?acceleration data request mismatch? error with an ?invalid accel request? response as specified in ta b l e 3 0 on the subsequent spi message only. no internal fault is recorded. the arming function will not be updated if an ?accelera tion data request mismatch? erro r is detected. the pcm output is not affected by the ?acceleration data request mismatch? error. register operations will be executed as specified in section 4.4 . 4.5.3.2 invalid register request the following conditions result in an ?invalid register request? error: ? an attempt is made to write to an un-writabl e register (writable registers are defined in section 3.1 , ta b l e 3 ). attempts to write to registers $09, $18, $19, $1a and $1b will result in an error. ? an attempt is made to write to a register while the endini t bit in the devcfg register is set ? this applies to all registers with the exception of the devctl register (only bits 6 and 7 can be modified) ? an attempt is made to read an un-readable register (readable registers are defined in section 3.1 , ta b l e 3 ). attempts to read registers $09, $18, $19, $1a and $1b will result in an error. the device responds to an invalid register request? error with an ?invalid register request? response as shown in table 30 . 4.5.4 device reset indications if the devinit, or devres bit is set in the devstat register as described in section 3.1.11 , the device will respond to ac- celeration data requests with an ?internal error present? response until the bits are cl eared in the devstat register. the devi nit bit is cleared automatically when device initialization is complete (reference t op in section 2.7 ). the devres bit is cleared on a read of the devstat register. the arming f unction will not be updated on acceleration data request commands if the devinit or devres bit is set in the devstat register. the pcm output is disabled if the devinit or devres bit is set. d q r d q r dq sclk spi data out shift register data out buffer miso miso err
sensor 52 freescale semiconductor, inc. mma65xx 4.5.5 internal error the following errors will result in an internal error, and set the ide bit in the devstat register: ? otp crc failure ? writable register crc failure ? self test error ? invalid internal logic states 4.5.5.1 crc error if the ide bit is set in the devstat register due to one or more of the following errors, the device will respond to accelerati on data requests with an ?i nternal error present? response until the ide bit is cleare d in the devstat register. ? an otp shadow register crc failure as described in section 3.2 ? a writable register crc failure as described in section 3.2 ? a clock monitor crc failure as described in section 3.4.2 the arming function will not be updated on acceleration data request commands if a crc erro r is detected. the pcm output is not affected by the crc error. if the crc error is in the writable regist er array, and the endinit bit in the devcfg register has been set, the error can only be cleared by a device reset. the ide bit will not be cleared on a read of the devstat register. if the crc error is in the otp shadow regi ster array, the error cannot be cleared. register operations will be executed as specified in section 4.4 . 4.5.5.2 self test error if the ide bit is set in the devstat register due to a self test activation failure, the device will respond to acceleration da ta requests with a ?self test error? response until the ide bit is cleared in the devstat register. the arming function will not b e updated on acceleration data request commands if a self test error is detected. the pcm output is not affected by the self test error. the ide bit in the devstat register will remain set until a read of the devstat register o ccurs, even if the internal fa ilure is removed. if the internal error is still present when the devstat register is read, the ide bit will remain set. register operations will be executed as specified in section 4.4 . 4.5.6 offset monitor error if an offset monitor error is present as described in section 3.8.5 , the offset_x or offset_y bit in the devstat register will be set. the device will respond to an acceleration request for the corresponding axis with an ?internal error present? res ponse until the offset_x or offset_y bit is cleared in the devstat register. the ar ming function will not be updated. once the error condition is removed, the offset_x or offset_y bit in the devstat regist er will remain set until a read of the devstat register occurs. the pcm output is not affected by th e offset monitor over range condition. register operations will be executed as specified in section 4.4 . 4.6 initialization spi response the first data transmitted by the device following reset is the spi error response shown in ta b l e 3 0 . this ensures that an un- expected reset will always be detectable. the device will respond to all acceleration data requests with the ?invalid accelerat ion data request? response until the devres bit in the devstat register is cleared via a read of the devstat register. the arming function will not be updated on acceleration data request commands until the devres bit in the devstat register is cleared.
sensor freescale semiconductor, inc. 53 mma65xx 4.7 acceleration data representation acceleration values are determined from the 12-bit digital output (dv) using the following equations: the linear range of digital values for signed data is -1920 to +1920, and for unsigned data is 128 to 3968. resulting ranges and some nominal acceleration values are shown in the following table. table 34. nominal acceleration data values unsigned digital value signed digital value nominal acceleration 105g 105g 120g 3969 - 4095 1921 - 2047 unused unused unused 3968 1920 80.000 g 105.49 g 120.00 g 3967 1919 79.958 g 105.44 g 119.94 g ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2050 2 0.083333 g 0.1099 g 0.1250 g 2049 1 0.041667 g 0.0545 g 0.0625 g 2048 0 0 g0g0g 2047 -1 -0.041667 g -0.0545 g -0.0625 g 2046 -2 -0.083333 g -0.1099 g -0.1250 g ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 129 -1919 -79.958 g -105.44 g -119.94 g 128 -1920 -80.000 g -105.49 g -120.00 g 1 - 127 -1921 - 2048 unused unused unused 0 0 fault fault fault acceleration sensitivity lsb dv 2048 ? () = acceleration sensitivity lsb dv = for signed data for unsigned data
sensor 54 freescale semiconductor, inc. mma65xx figure 38 shows the how the possible output data codes are determ ined from the input data and the error sources. the rele- vant parameters are specified in section 2.4 . figure 38. acceleration data output vs. acceleration input
sensor freescale semiconductor, inc. 55 mma65xx 5package 5.1 case outline drawing reference freescale case outline drawing # 98asa00090d http://www.freescale.com/files/shar ed/doc/package_info/98asa00090d.pdf 5.2 recommended footprint reference freescale application note an3111, latest revision: http://www.freescale.com/files /sensors/doc/app_note/an3111.pdf table 1. revision history revision number revision date description of changes 3 03/2012 ? added safeassure logo, changed first paragraph and disclaimer to include trademark information. ? added devices to ordering table: MMA6519KW, mma6525kw and mma6527kw
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com mma65xx rev. 3 03/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. safeassure an d xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. all rights reserved.

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